Burst transfer is a conventional technique for enabling a data processing apparatus to transfer data at high speed. Among burst transfer techniques, one technique is known that when a request for a transfer of different data having a high priority level is created during data transfer, the burst width of the data under transfer is set to a width that allows the data to be transferred before the start of transfer of the different data having the high priority level. Another technique is also known that when multiple data are transferred by time-shared parallel processing, the time within which transfer of data should be completed and a time expected to be consumed for transferring the data are calculated and based on the result of the calculation, the rate of time-sharing for data transfer is adjusted dynamically. For example, see Japanese Laid-Open Patent Publication Nos. 2007-304908 and 2006-209500.
According to the conventional burst transfer techniques, however, memory engaged in burst transfer cannot be accessed for purposes other than burst transfer. For this reason, if a processor tries to access the memory engaged in burst transfer, the processor has to stand by until the burst transfer ends. When the volume of data to be transferred is large, burst transfer to the memory is repeated. As a result, the stand-by time of the processor may get longer if the timing of the access is not good. This leads to a problem in that the effective capacity of the processor deteriorates.
If the burst width representing the size of data transferred in one burst transfer is reduced, the time required for one burst transfer becomes shorter. As burst transfer is repeated, therefore, the number of times that the memory returns to a state of being accessible for other purposes increases, thereby facilitating access by the processor. However, a smaller burst width leads to an increase in the number of times that burst transfer carried out until the completion of transfer of data to be transferred. This increase in the number of times of burst transfer results in an increase in delay times preceding data output from the memory and in the time required for pre-charge. Hence, the capability of processor to access the memory deteriorates.
If the interval between burst transfers is widened, the period in which the memory returns to a state of being accessible for other purposes increases between one burst transfer and the next burst transfer, thereby facilitating access of the memory by the processor. However, when the processor accesses the memory while the memory is engaged in burst transfer, the processor has to stand by until the burst transfer ends. Hence, the deterioration of effective capability of the processor cannot be prevented.